JTAG 동작

http://www.inaccessnetworks.com/projects/ianjtag/jtag-intro/jtag-intro.html

All the signals between the chip's core logic and the pins are intercepted by a serial scan path known as the "Boundary Scan Register" (BSR), and shown as cells "C0", "C1", "C2", "C3", and "C4" in the figure above. In normal system operation this path can transparently connect the core-logic signals to the pins and effectively become invisible. In external-test mode, it can disconnect the core-logic from the pins, drive the output pins ("Pin1", and "Pin2" in the figure above) by itself, and read and latch the states of the input pins (figure: "Pin0", and "Pin2"). In internal-test mode, it can disconnect the core-logic from the pins, drive the core-logic input signals by itself, and read and latch the states of the core-logic output signals.